High sample rate array architectures for median filters

This paper presents high sample rate semi-systolic array architectures for computing 1-D and 2-D non-recursive and recursive median lters. A high sample rate is obtained by pipelining the computations in each processor. While the non-recursive lters are pipelined by placing latches in the feed-forward paths, the recursive lters are restructured to create additional delays in the feedback paths, and then pipelined using the delays as latches.